J. Jean Jenifer Nesam ¹, Sivanantham Sathasivam ¹

Affiliations
1 School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Background:Floating point (FP) multiplication has found its importance in many microprocessors but it is very difficult to implement on FPGA because of its complicated internal computation. Methods:We investigate partial product (PP) reduced FP multiplication based on Radix-4 Booth Encoded Algorithm (BEA). Radix-4 BEA reduces the number of PP generation by half. PP reduction performed in three steps such as Grouping bits (3-bit for each group), Encode the group and PP calculation for each group. Findings:The investigation results show that Radix-4 BEA works perfectly on signed multiplication and unsigned (FP mantissa) multiplication needs some extra consideration. Radix-4 BEA grouping multiplier bits need overlapping one bit from both adjacent group that limits block and parallel processing. 2’s complement calculation and sign extension essential for PP generation that increases the resource utilization. In this paper, 32 bit improved FP multiplication based on classical recoding and parallel processing method is proposed. Classical recoding reduces PP generation by half without overlapping, sign extension and 2’s complement. 24 bit mantissa split into blocks (8 bit each) and each blockis recoded using classical recoding algorithm and all blocks are performed in parallel. Applications: The experimental results show that our proposed design runs with high frequency with less resource utilization and suitable for signal processing applications.   

Keywords

Floating point multiplier, single-precision, classical recoding, parallel processing, block multiplication.

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Sivanantham Sathasivam ¹, G. Venu Reddy ¹

Affiliations
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Objectives: This paper aims at designing high speed and high throughput Fast Fourier Transform (FFT) processor which is a critical block and is widely used in many Digital Signal Processing applications. Methods: The proposed model works with both real and complex type of input data. Pipelining in the proposed architecture is achieved with single delay feedback methodology. Findings: The CMOS 0.18 µm is used to design Application Specific Integrated Circuit (ASIC) for the proposed FFT processor and it works with an input size of 36 bits at the operating frequency of 100 MHz, occupies an area of 1.27 mm and consumes 39 mW, at an operating voltage of 1.8V.Obtained results are compared with existing methods in terms of input word length, throughput, power dissipation and it shows that the proposed architecture gives high throughput, uses 3x more word length and 2x less power dissipation. Applications: The designed chip can be used in scientific computations since it require less power and operates in high speed.

Keywords

ASIC, Fast Fourier Transform, Pipelining, Single Delay Feedback, Throughput

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Sivanantham Sathasivam ¹, S. Khaja Rahamathulla ¹

Affiliations
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Background/Objectives: Digital communication is the process of transmission of the information which had been encoded digitally at the transmitter side and then passed through the channel encoder followed by the digital decoder at the receiver end. This paper majorly concentrated on low power synthesis and power analysis of HDB3 encoder. Methods: Alternative Mark Inversion (AMI) is a well-known data encoding technique for data encryption. HDB3 encoding is a derivative of AMI (Alternative Mark Inversion) encoding. The HDB3 code is one of the best representation codes which satisfies all the conditions of AMI and improves the limitations of AMI. Findings: The HDB3 encoder is designed with the help of V and B modules. It encodes consecutive zeros by inserting V and B in the form B00V. The VLSI architecture of the HDB3 encoder is implemented in Verilog HDL and the proposed design is synthesized and the results are compared with different TSMC technology libraries. The physical design of the chip is carried out in Cadence SoC Encounter tool. Low power synthesis results shows that the power required for the design is 17.65µW in 45nm technology. Applications: It has the ability to perform functions like Error correction/detection, provides better data encryption techniques in digital communication.

Keywords

AMI (Alternative Mark Inversion), Data Encryption, Encryption, HDB3, V and B Module

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